The invention relates generally to imaging sensors and more particularly to an imaging sensor utilizing CMOS active pixels.
Solid-state imaging sensors are utilized in telescopes, digital cameras, facsimile machines, scanners, and other imaging devices. An imaging sensor captures an image by converting incident light reflected from the image into electrical signals in an analog form. A typical imaging sensor has an array of xe2x80x9cpixelsxe2x80x9d or discreet regions, each pixel containing a light sensitive element. Each light sensitive element generates an electrical signal which is proportional to the intensity of the incident light on that pixel. The electrical signals from all the pixels are converted into digital form and stored in memory. The digitized image data can then be displayed on a monitor, printed onto a sheet of paper, or analyzed for information concerning the properties of the image.
Conventional imaging devices use what are commonly known as xe2x80x9ccharge coupled devicesxe2x80x9d (CCDs) in imaging sensors. A CCD utilizes the properties of a metal-oxide semiconductor (MOS) to create a capacitor at each of its pixels. The capacitor on a CCD is able to accumulate electrical charge generated by the incident light. The accumulated electrical charge is then transferred as an electrical signal to off-chip circuitry, such as an analog-to-digital converter (ADC) and memory.
Although CCDs have many strengths, including high sensitivity, CCDs also have a number of weaknesses. One significant weakness is that CCDs require a substantial amount of power for external control signals and large clock swings. Another significant weakness is that on-chip integration of electronic devices is very difficult to fabricate on CCDs. In addition, CCDs require specialized fabrication processing that is more expensive than conventional MOS fabrication.
Due to the weaknesses of CCDs, another type of imaging sensors has developed. These imaging sensors are known as active pixel sensors (APSs). Unlike CCDs, APSs use mainstream complementary metal-oxide semiconductor (CMOS) technology for fabrication. In addition, APSs more readily accommodate on-chip circuitry along with the light sensitive elements, such as on-pixel amplifiers, timing and control circuits, multiplexers, and ADCs. APSs also require significantly less power to operate.
U.S. Pat. No. 5,461,425 to Fowler et al. (hereinafter Fowler), entitled xe2x80x9cCMOS Imaging Sensor with Pixel Level A/D Conversion,xe2x80x9d describes an imaging sensor with on-pixel ADC circuitry on a single semiconductor chip. The imaging sensor of Fowler has an array of pixels, with each pixel including a phototransistor and an ADC. The analog signal generated by the photo-transistor is converted to a serial stream of bits of digital data by the on-pixel ADC. The digital data is then filtered and stored in an external memory. The on-pixel ADC is described as having the advantage of minimizing parasitic effects and distortion caused by low signal-to-noise ratio.
Another imaging sensor of interest is described in U.S. Pat. No. 5,665,959 to Fossum et al. (hereinafter Fossum), entitled xe2x80x9cSolid-State Image Sensor with Focal-Plane Digital Photon-Counting Pixel Array.xe2x80x9d The imaging sensor of Fossum includes a top semiconductor chip which is xe2x80x9cbump bondedxe2x80x9d to a bottom semiconductor chip. The top semiconductor chip includes photo-detector diodes with corresponding unit cells, with each unit cell containing a buffer amplifier circuitry. The bottom semiconductor chip includes digital counters and may also include an accumulator (buffer memory).
What is needed is an imaging sensor having on-chip circuitry that accommodates compactness and signal manipulation.
An imaging apparatus and a method of capturing and storing an image in digital form within a photosensitive area include integrating an array of memory cells within each pixel of the photosensitive area. In the preferred embodiment, the arrays are formed on a monolithic structure and each array contains a sufficient number of memory cells to store an 8-bit or more digital word that is representative of the intensity of incident light that is reflected from the image. In the more preferred embodiment, the array has the capacity to store an additional 8-bit or more digital word. The additional word could represent a reference signal that can be used for fixed pattern noise cancellation.
Preferably, all of the memory cells within each pixel are dual port memory cells fabricated on a semiconductor chip. The dual port memory cells allow for independent write and read operations. For example, in a single pixel, the writing operations for all the memory cells can be performed simultaneously (i.e., in a parallel manner), while the read operations can be performed in a serial manner.
Each dual ported memory cell may be a dynamic random access memory (DRAM) cell formed by a write port, a storage element, and a series gated read port. The dual ported memory cell can be formed by a series connection of four devices, such as four transistors. Alternatively, the dual ported memory cell can be formed by a series connection of three devices and a capacitor, such as three transistors and a planar, a stacked, or a trench capacitor. In the four-transistor embodiment, one transistor functions as a capacitor to store a charge that is indicative of the value of a bit of the pixel data. On one side of the storage device is a write access device that is manipulated during a write operation to connect the storage device to a write bit line from which the digital word data is received. Connected to the same storage device are two series connected read devices that are separately controlled to read data to a local read bit line. The series connected read devices function as a local read decoder. The bit of digital word within the storage device is read only when both of the read devices are conducting. The configuration of the dual port memory cell accommodates the independent read and write operations.
Furthermore, each pixel contains an on-chip photosensitive element, such as a photodiode. Preferably, the photodiodes are of alpha-silicon or a carbon polymer type. In the preferred embodiment, the photo-diodes are utilized to generate both photo signals and reference signals that are representative of dark frames used for the fixed pattern noise cancellation.
Also included in each pixel is an on-chip comparator which is utilized in part for an analog-to-digital (A/D) converting operation. The comparator is supplied with an A/D reference signal from on-chip peripheral circuitry. In the preferred embodiment, the A/D reference signal is a ramp signal from a ramp generator that is a part of the on-chip peripheral circuitry for the pixels. The comparator operates in unison with the ramp generator and a counter, which is also a part of the peripheral circuitry, to capture and store a digital count word generated by the counter in the memory array within each pixel. The peripheral circuitry may also include control and timing circuitry as well as an amplifier, a register, and an arithmetic circuit for the fixed pattern noise calculations.
In operation, the comparator in each pixel compares the ramp signal to the photo signal generated at that pixel. Simultaneously, the counter begins counting and supplying the pixel with the digital count word. One ramp signal and one series of digital count words are utilized by all the pixels in the matrix of the imaging apparatus. As an example, the digital count word could be eight bits wide for a count of two hundred fifty-six. When the ramp signal matches the photo signal, the comparator captures the last digital count word in a first row of memory cells within each pixel. The captured digital count word represents a digital photo signal word or the photo signal in a digital form.
In the preferred embodiment, the capturing-and-storing operation is performed a second time for xe2x80x9cdouble sampling.xe2x80x9d The second sampling involves generating and converting a reference signal, and storing the reference signal in digital form. The digital reference signal is stored in a second row of memory cells in each pixel.
One advantage of the invention is that the photo signal is captured in each pixel in a parallel manner. This is accomplished by utilizing one ramp signal and one series of counts from the counter along with the memory array within each pixel that can store an entire digital word. All the photo signals in the pixels are compared at the same time. Thus, the rate of A/D conversions for all the photo signals is significantly increased. Consequently, the electronic shutter speed is increased, since the shutter speed is dependent upon the rate of A/D conversions.
Another advantage of the invention is that the difficulties typically associated with transferring an analog signal to a digital frame buffer memory are eliminated by on-chip A/D converting and on-chip storing the image information within the array of pixels.